BIST

A implement of low power BIST based on test segment transformation

基于测试片段间转移的低功耗BIST实现

Design and Simulation of Memory BIST Based on March C + Algorithm

基于MarchC+算法的存储器内建自测试自测试设计与仿真

Unit Test Framework Based on BIST Software Test Idea

基于BIST软件测试思想的单元测试框架

Besides , discusses the application of BIST in memory test .

此外，还对BIST测试技术在存储器测试中的应用进行了探讨。

A Partial Scan Algorithm for BIST Based on Structure Analysis and Testability Analysis

一种基于结构和可测性分析的BIST部分扫描算法

The Research and Design BIST Based All Status Pseudo-Random Sequence Generators

基于全状态伪随机序列的BIST设计

Research on key techniques in BIST implementation for logic cores .

应用于逻辑核的BIST关键技术研究。

Design of low power consumption of BIST based on optimized LFSR

基于LFSR优化的BIST低功耗设计

Mixed - signal circuit BIST based on spectral analysis

谱分析方法的混合电路BIST

An approach for testing FPGA logic cells based on BIST

基于BIST的FPGA逻辑单元测试方法

Design of ARMA Module Based on BIST Technology of Analog Integrated Circuit

基于模拟集成电路BIST的ARMA模块设计

A Fault Diagnosis Strategy Based on BIST Matrix Scan for VLSI

基于BIST矩阵扫描的一种VLSI故障诊断策略

Simulated annealing algorithm applied in low power BIST scheme

模拟退火算法在低功耗BIST中的应用

BIST Structure and Test Vector Generation Based on a Controlled LFSR

一种基于受控LFSR的内建自测试结构及其测试矢量生成

BIST theory , solution and application in FPGA are studied in this thesis .

本论文主要讨论的是可编程逻辑器件FPGA的BIST理论、方法和应用。

Low Power Design of Mixed-mode BIST Based on Folding Set

基于折叠集的混合模式BIST的低功耗设计

BIST Algorithm Studies Considering Time Delay on FPGA Device

考虑时延的FPGA器件BIST算法研究

Application of BIST in the embedded software test

BIST在可信性嵌入式软件测试中的应用

Design of the Floating Point Adder and Research of Its Bist

FPU中浮点加法器的设计及其内建自测试的研究

BIST Scheme Based on Two-Dimensional Test Data Compression

基于二维测试数据压缩的BIST方案

Deterministic and Low Power BIST Based on Scan Patterns Partition

应用向量划分的低功耗确定性BIST方法

BIST Scheme for Test Data Sharing with Multiple Cores

一种多核共享测试数据的BIST方案

BIST is applied in embedded software test .

本文论述了BIST在可信性嵌入式软件测试中的应用。

A New Low Power Design of Mixed-mode BIST

一种新型混合模式BIST的低功耗设计

A BIST Scheme Based on Selecting State Transition of Folding Counters

一种选择折叠计数状态转移的BIST方案

Low Power Technology of BIST Testability Design

BIST可测性设计的低功耗技术

Work focuses on test algorithm , design , usage and BIST based on BST.

重点对基于边界扫描的测试算法、设计、应用和基于其上的BIST设计进行了研究。

Research on Low Power Deterministic BIST Based on Genetic Algorithm-Folding Counter

基于遗传&折叠计数的低功耗确定BIST研究

An All - Digital BIST Scheme for the ADC Test

全数字的模数转换器内建自测试方案

This BIST structure has a little influence on the inner multiplier structure and its speed .

所实现的测试结构对乘法器的内部结构和运算速度影响很小，而且测试结构所占的比例也很小。