floorplan

An Overview of Integrating High Level Synthesis and Floorplan

高层次综合与布图规划相结合的方法与技术

VLSI floorplan optimization design with soft blocks

带软模块的VLSI布图规划优化设计

The research on " integrating high level synthesis and floorplan " is a very important part in the research on electronic design automation .

介绍了高层次综合与布图规划相结合的基本方法与技术及其研究进展。

Implement floorplan for VLSI with object-oriented methods

用面向对象方法实现VLSI布图规划

Simultaneous Allocation and Floorplan Algorithm

一种同时进行资源分配和布局规划的高层次综合算法

During the partition procedure , floorplan informations are used to direct allocation , thus interconnections are efficiently optimized .

在算法进行过程中可以不断利用前面步骤所提供的布局信息指导资源分配，从而有效的对连线进行优化。

Ant colony algorithm for floorplan

平面布局的蚁群算法

This Paper presents the detail designation and introduces a verification flow for the structure proposed . Floorplan and partly verification is done at last .

本文详细的介绍了该结构的设计实现以及对该结构进行的验证方法，并在最后对所得到的结构进行了布局布线和部分验证。

This thesis contains : 1 . As the key step of the physical design , floorplan will influence the effect of the placement and routing directly .

本文主要工作包括：1.布局规划作为物理设计中的关键步骤，其好坏直接影响布局布线的效果。

In the section of Floorplan and Place , it focuses on power supply network design and optimization , which is the key point for chip working stably .

在版图规划和布局中，重点研究了电源网络设计和优化，这是芯片稳定工作的基础。

On this basis , the calculations of material balance in the production process and equipment selection were completed . Finally , the flow chart and floorplan were drew .

根据试纸条的研制试验，确定工艺流程，在此基础上完成了试纸条生产过程中的物料衡算和主要生产设备选型，最后绘制了工艺流程、车间平面布置等图。

As the early stage of VLSI physical design , floorplan / placement not only determines performance of a circuit directly , but also influences the following routing stage greatly .

布图规划和布局是VLSI物理设计中的早期阶段，其结果不但直接影响VLSI的整体设计质量，而且会对后续的布线设计产生决定性的影响。

In the experimental process , firstly we complete the layout design flow , including Synthesis , Floorplan , Placement , CTS ( clock tree synthesis ) and Route .

在实验过程中，首先完成对电路设计的综合、布图规划、布局、时钟树综合以及布线等版图设计流程。

In addition , cooperating with other group members mutually , we had made a simple electric circuit layout system which is composed of partitioning algorithm , floorplan algorithm and placement algorithm etc.

除此之外，通过与研究小组的成员合作，将本算法与划分算法，详细布局算法等集成了一个简单的电路布局系统。

The outlet looked quite deserted in a way and the floorplan was not very clear . I saw quite a few guests wandering around to find the way .

卖场看上去很荒芜的样子，卖场的平面图又不清晰，我看到不少游客都在那边绕了半天还找不到北的。

The digital one includes SPEC , Verilog coding , simulation , synthesis , floorplan , routeing , static timing analyze and DRC / LVS check .

数字电路设计流程则包括：制定SPEC，Verilog代码编写，仿真，逻辑综合，布局，布线，静态时序综合和DRC／LVS检查。

Many effective methods were tried in Floorplan , Placement , Clock synthesis and Routing , and the final layout of the digital part of Ethernet controller chip was presented in this chapter .

布局规划、布局、时钟树综合和布线借鉴了一些实用有效的方法，并在论文中给出了以太网控制器芯片的数字部分的最终版图。

The synthesis is achieved by creating connection boxes and switch boxes according to the routing channel width given in the structural description . The floorplan method is a tile-based one .

其中逻辑综合方法主要包括根据结构描述中指定的布线通道宽度生成布线资源中的基本单元如连接盒、开关盒等。

A Group-Based Timing-Driven Floorplan Method

一种基于组的时序驱动布局规划方法

Second , based on the first point , the author has a deep research on hot problems in physical design flow such as high powerful clock routing , floorplan , place and route , power plan and optimization , parastic extraction and so on .

其次，在此基础上，对物理设计流程中的热点问题，诸如：高性能时钟布线、布图规划、布局布线、电源分布网络的设计与优化及寄生参数的提取等，进行了较为深入的研究。

This paper proposes a timing-driven floorplan method based on groups in the physical design . This method employs available EDA tools and partitions the netlist into groups , and then utilizes the architecture experience of designers to layout , adjust and optimize the netlist .

本文提出了一种基于组的时序驱动布局规划方法，它利用现有的EDA工具将网表划分为组，并充分利用设计师的体系结构经验进行布局、调整和优化。

A FIR filter circuit and real world IDCT decoder circuit are used to test the new algorithm ; the experimental results show that the total delay of the circuit was optimized by 8 % . A new algorithm for high level re-scheduling after floorplan is presented in this thesis .

论文中通过fir滤波器和实际的IDCT解码器对算法进行了验证，实验证明算法可以对电路达到8%的电路性能改进。提出一种新的布图规划后高层次再调度算法。