soft-core

Design of an Ethernet Interface Based on the Nios Soft-core Processor

基于Nios软核处理器的以太网接口设计

This paper proposes a new method for embedded system designing , based on FPGA and soft-core CPU .

提出了一种基于FPGA（现场可编程门阵列）和软核CPU的嵌入式系统设计的新方法。

Study on power press roll device for peeling rotten and soft-core logs

腐软芯材旋切动力压辊装置的研究

Research and Design of Soft-core IP for AVS Inter Decoder

AVS帧间解码IP软核的研究与设计

Astronomical IRFPA Image Collecting System Based on the Nios ⅱ Soft-core Embedded Processor

基于NiosⅡ嵌入式软核处理器的天文用IRFPA图像采集系统

Implementing the synchronization of industrial Ethernet precise clock based on Nios II soft-core

基于NiosⅡ软核的工业以太网精确时钟同步的实现

Research and Design of Nios ⅱ Soft-core Processor

NiosⅡ软核处理器的研究与设计

Design and Implementation of Multi-channel Phone-billing-system Based upon NIOS Soft-core CPU

基于NIOS软核CPU技术的多路电话计费系统的设计与实现

With the development of high speed image processing , the soft-core processing technology of image processing system has become a hotspot of research .

随着高速图像处理技术的应用领域不断扩大，对图像处理速度的要求也越来越高，当前基于软核处理器的图像处理系统成为研究的热点。

Implementation of Soft-Core Processor and DDFS Based on FPGA

基于FPGA的软核处理器及DDFS实现

In addition the study showed that people who viewed soft-core images often were less likely to hold positive views of women .

此外研究发现，经常观看软核女性形象的人对女性更不易有正面的看法。

Design and Implementation of 5Gbps ~ 40Gbps Broad Band Switch Soft-core

5Gbps～40Gbps宽带交换软核的设计与实现

This paper researches the implementation methods of the 5Gbps ~ 40Gbps switch technology and IP soft-core .

研究了5Gbps~40Gbps交换技术和IP软核的实现方法。

NIOS ⅱ soft-core processor is a flexible and efficient embedded processor promoted by Altera Corporation .

NIOSⅡ软核处理器是Altera公司推出的一款灵活高效的嵌入式处理器。

Designed the inter-frame decoding IP soft-core , including the motion vector generation module , prediction processing modules and interpolation modules .

详细设计了帧间解码IP软核，包括运动矢量生成模块、预测处理模块和插值模块。

A 40Gb / s switch IP soft-core with self-dependence intellectual property was realized .

形成了具有自主知识产权的40Gb/s交换IP软核。

The Nios ⅱ soft-core processor improve the integration of the system and is helpful to the miniaturization of instrument .

NiosⅡ软核处理器提高了系统的集成度，有利于系统的小型化，降低了成本。

The design and implementation of CPU soft-core is necessary for SoC design since the soft-core can be tailored to fit actual applications .

CPU软核可以根据实际应用需要进行剪裁，因而CPU软核设计是SoC设计实现的重要部分。

Nios II soft-core processor implanted into FPGA as the control chip controls and preprocesses the data of the entire image acquisition system .

采用FPGA作为控制芯片，在其中植入NiosⅡ软核处理器以对整个图像采集系统的数据进行控制和预处理。

The prototype designs with soft-core processors of Nios II in FPGA , improves the programmability of network processors .

网络处理器芯片原型采用NIOSii软核处理器在FPGA上实现，提高了网络处理器的可编程能力。

I distinctly remember my high school self , wide-eyed , poring over the soft-core Starr report with friends .

我还清楚地记得高中时代的我，睁大了眼睛，和朋友们一起狼吞虎咽地读着《斯塔尔报告》（StarrReport）中那些香艳的内容。

It inherits the hardcore , soft-core , DSP , memory , peripheral I / O and programmable logic .

它继承了硬核、软核、DSP、存储器外围I∕O及可编程逻辑。

Implementation of Nios soft-core in DTV Modulator

Nios软核处理器在DTV调制器中的实现

With the establishing of verification and test platform for SDH chip , We realize the function simulation , timing simulation and performance test of the IP soft-core .

通过建立SDH芯片验证平台和SDH芯片测试平台，实现IP软核的功能仿真、时序仿真和芯片性能测试。

The switch IP soft-core is of high quality , steady performance and flexibility which accords with the design requirements of the swith IP soft-core .

使得IP软核质量优良、性能稳定，适应性强，达到了交换IP软核的设计要求。

The Design of 8-bit Turbo-51 's CPU Soft-core

一款8位Turbo-51的CPU软核的设计

According to the structure model of data acquisition and processing system connected by Ethernet , the network interface module based on the Nios soft-core system is designed to construct the network data acquisition system .

为构建网络化的数据采集系统，根据数据采集模块与处理控制模块通过以太网相连接的结构模型，设计了基于Nios软核系统的嵌入式以太网网络接口模块。

Based on this method , the techniques of both reducing and extending the instruction set of the 8051 soft-core CPU by modifying the VHDL source code are thoroughly studied .

文中分析了对应用程序进行指令统计的方法，重点介绍了通过修改HDL文件对8051软核CPU指令集进行删减和扩充的技术。

For the digital part , this design is mean to construct the SOPC system in the FPGA , embedded Nios II soft-core processor to control the operation of the entire system .

对于数字部分，在FPGA内构建SOPC系统，嵌入NIOSii软核处理器对整个系统进行控制。

In practice , the designer can use this soft-core as a communication module through the FPGA implementation or to quickly build a Field Bus communication system to realize flexible CAN bus interface solutions .

在实际应用中设计者可以将此软核作为通讯模块通过FPGA实现，或者快速搭建现场总线通信系统，实现灵活的CAN总线接口方案。