内建自测试

内建自测试（BIST）是一种有效降低测试开销的技术，在瞬态电流测试中得到了应用。

BIST has been applied into transient current testing as an effective method to reduce testing spending .

基于内建自测试的伪随机测试向量生成方法

The Pseudorandom Test Pattern Generation for BIST

基于MarchC+算法的存储器内建自测试自测试设计与仿真

Design and Simulation of Memory BIST Based on March C + Algorithm

基于FPGA的内建自测试的实现研究

Research for Built-In Self-Test Based on FPGA

针对嵌入式Cache的内建自测试算法

Built-In Self-Test Algorithm for Embedded Cache

本文论述了两种适合SoC芯片中嵌入式flash存储器的内建自测试设计方案。

In this paper we present two BIST approaches suitable for embedded flash memory testing in a SoC environment .

嵌入式双端口SRAM可编程内建自测试结构的设计

Design of Programmable Memory BIST for Embedded Dual Ports SRAM

一种改进的嵌入式SRAM内建自测试设计

An Improved Design of Embedded SRAM Built-In Self Test

存储器内建自测试（MemoryBuilt-InSelf-test，MBIST）是一种有效的测试嵌入式存储器的方法。

MBIST ( memory built-in self-test ) is very effective in testing embedded memories .

本文提出了一种系统芯片（SoC）中用于降低内建自测试（Built-InSelf-test，BIST）峰值功耗的调度算法。

A low peak power consumption Built-in self-test ( BIST ) scheduling algorithm for system-on-a-chip ( SoC ) is presented .

针对IP软核的测试、验证提出了面向测试、验证的IP软核设计方法&BIST内建自测试方法。

For the test and verification of soft-IP , the paper presents a solution of Design For Test technique , of which the BIST ( Built-in Self Test ) is described in particular .

在现在的主流可测性技术中，内建自测试技术（Built-InSelf-Test，BIST）是一种节省时间、降低成本的方法。

Among the current testing technologies , Built-In Self-Test ( BIST ) is a both time-saving and cost-saving means .

针对混合信号电路的测试问题，提出了一种内建自测试（BIST）结构，分析并给出了如何利用该结构来计算计算片上高速模数转换器（ADC）的静态参数。

Aiming at the mixed-signal circuit testing , an integrated BIST architecture for testing on-chip high speed ADC was presented .

一种基于受控LFSR的内建自测试结构及其测试矢量生成

BIST Structure and Test Vector Generation Based on a Controlled LFSR

SATA内建自测试的电路设计与实现

Design and Realization of SATA Build In Self Test

FPU中浮点加法器的设计及其内建自测试的研究

Design of the Floating Point Adder and Research of Its Bist

本文重点设计基于状态机控制的SRAM内建自测试电路。

This paper focuses on the overall design of an SRAM BIST circuit based on Finite State Machine ( FSM ) .

作为结构化可测性设计策略（structureddesignfortest）的一种，存储器内建自测试（MemoryBuilt-InSelf-test，MBIST）已经成为当前针对嵌入式随机存储器（E-RAM）测试的一种经济有效的途径。

As a kind of the structured design for test techniques , memory built-in self-test ( MBIST ) is a cost-effective approach for the embedded RAM testing .

在设计中，采用内建自测试的方法，各个模块通过VHDL语言描述，并且在QUARTUSII环境下实现仿真。

In the design , using built-in since test method , the various modules by VHDL language description , and in Quartus II environment realize simulation .

软件内建自测试（Build-In-Self-Testforsoftware）的思想来自于硬件内建自测试。

The concept of BIST ( Built-In-Self-Test ) for software comes from BIST for hardware and a project National Nature Science Foundation of China .

内建自测试（BIST）作为一种有效的测试技术可以大大地降低测试开销。

Built-in self-test ( BIST ) is used as an effective test technique and it can greatly reduce test overheads .

另外，本文还针对IP核投片测试提出一种扫描测试电路结构，能够实现测试芯片的扫描测试和高速内建自测试（BIST）。

Moreover , a scan test circuit was proposed . This circuit can implement scan test and high speed build in self test ( BIST ) for IP core chip tests .

然后介绍了各种测试技术的原理及特点，包括边界扫描测试、嵌入式核测试及内建自测试（BIST）。

Then this paper gives an introduction of different DFT principle and characteristic , such as boundary scan test , embedded core test and BIST .

其次，结合伪随机测试原理及MarchC算法完成了基于FPGA的随机逻辑和嵌入式存储器的内建自测试电路设计和仿真，并采用特征分析法实现对测试响应信号的压缩和分析。

Secondly , design and simulation of FPGA-based random logic and embedded memory BIST circuit were completed based on pseudo random testing theory and March C algorithm , and characteristic analysis was used to realize the compression and analysis of testing response signal .

内建自测试模块提供两种测试模式可以用来测试DDR2芯片的好坏。

Built-in self test module provided two test modes that can be used to test the DDR2 chip good or bad .

本文通过曼彻斯特编码译码器IP核的设计、测试，介绍了广泛应用于IP核测试的方法&内建自测试（Built-inSelfTest）方法，强调了面向IP测试的IP核设计有关方法。

This paper introduces Built-In Self Test ( BIST ) method which can be widely used in IP Cores testing through describing the design and test of Manchester Encoder and Decoder IP Cores . The test-oriented techiques for testing the IP Cores are underlined also .

本文在对目前主要的可测性设计方法进行研究的基础上，根据所设计CPU的结构特点，采用了边界扫描技术和基于BILBO的内建自测试技术结合的可测性设计方案。

Based on the research of primary DFT method and the structure characteristic of designed CPU , the article combines the boundary scan and Build-In Self-Test based on BILBO to test .

片上网络FIFOs的内建自测试方法研究

Research on BIST test method for network-on-chip FIFOs

针对寄存器传输级（RTL）数据通路，文献[1]提出了两种功耗限制下非扫描内建自测试（BIST）方法。

In particular , the increased delay may cause delay faults . paper [ 1 ] proposed two power-constrained non-scan BIST methods for register transfer level ( RTL ) data paths .

为压缩内建自测试（BIST）期间所需测试数据存储容量，提出了一种新的基于测试数据两维压缩的BIST方案。

To reduce the storage volume of the test data during the built-in self-test ( BIST ), a new BIST technique based on two dimensional compression of test data is presented .