多位数

提出了一种基于电流模技术的动态元件匹配方案，用以实现∑ΔADC中内部多位数-模转换器（DAC）。

A dynamic element matching algorithm depending on current mode technology was presented for multibit internal ∑Δ converter .

讨论了智能计算机辅助教学（ICAI）系统的特点和机器学习的实现方法，并通过多位数的认识教学系统的编制，基本实现机械学习这一功能。

This paper discusses the features of the ICAI system and the realization method of machine learning . The function of machine learning can be realized by programming the instruction system of multi digit recognition .

多位数频标测量系统

A measurement system of non - integral frequency standard

三类多位数的积的捷算法

Three Types of Short - cut Calculation for the Product of Multi - number

这就要求用于多位数相加的加法器具有三个输入端。

This process requires that the adder used in multibit addition handle three inputs .

汇编实现一位数加数，多位数加法，查找字符串，乘法。

Achieve a compilation of several augend , multi-digit addition , search strings , multiplication .

两个多位数乘积的计算，通常可用乘法器或累加器自动实现。

Multiplier or counter-type adder can be usually used to realize the multiplication of two multidigit figures .

在数与代数板块，小学生对数的运算表现较好，而对多位数的认识及其应用，表现较差。

Findings : ( 1 ) In Number and Algebra , pupils do better in arithmetic than in multi-digit knowing and applying .

当两个多位数相加时，每一位的进位应与高一位数相加。

In the addition of two multibit numbers , the carry of each single bit addition is added to the next-insignificance bit .

十位以上数字是3或6的多位数的积的捷算法

Short - cut Calculation for The Product of Two Multi - digit Number Their Ten 's and over Place are all 3 or 6

在数学课程方面，孩子们应该不用纸笔便能做多位数乘除法。

In math curriculum , children will be expected to do multiplication and division with large numbers without the use of pen and paper .

在一位数加多位数不进位加法口算中，口算时间差异主要源于运算时间差异和整合时间差异；

In the non-carry mental addition of 1-digit number and multi-digit number , mental arithmetic time differences lie in arithmetic time differences and integration time differences .

在多位数减一位数不借位减法口算中，运算时间年级差异不显著，而整合时间存在显著的年级差异；

In the mental subtraction of multi-digit number subtracting 1-digit number , there are no grade differences of arithmetic time and there are significant grade differences of integration time .

所用的方法是，将相加两数的各位同步地输入到加法器中。这就要求用于多位数相加的加法器具有三个输入端。

The concept used is that the bits of the two numbers to be added are made available to the adder synchronously . This process requires that the adder used in multibit addition handle three inputs .