时钟周期

暂停（Stall）&处理器不开始执行新指令处的时钟周期。

Stall & A clock cycle where the processor does not begin a new instruction .

采用桶形移位器、基于PLA的并行解码算法等方法使得每个时钟周期解一个变长码码字。

The design uses barrel shifter and PLA-based parallel algorithm so that one variable length code can be decoded in every clock cycle .

DSP可以在一个时钟周期内完成移位。

A DSP can complete this shift with one cycle .

运行CPC的最简单方式是收集系统时钟周期，其事件名是SystemClockCycles或C。

The simplest way to run CPC is to collect system clock cycles , whose event name is System_Clock_Cycles , or C.

基于时钟周期的VHDL模拟算法

A cycle based algorithm for VHDL simulator

通过硬件在一个时钟周期内直接执行Java虚拟机（JVM）中大多数简单的算术／逻辑指令；

It can execute most of simple java virtual machine ( JVM ) arithmetic / logic instructions in one clock period in hardware .

采用自顶向下的设计方法，划分了子模块，对各子模块进行仿真，进行了FPGA综合，对宏块滤波所需时钟周期进行了分析。

We do the simulation for each sub-module . At last we do FPGA synthesis and analyze the clock cycles required for the macro block filter .

此程序调用了ncpu，其中包含函数“engine（）”，此函数耗尽了CPU上的CPU时钟周期。

The program called ncpu has a function " engine ()" which uses up CPU cycles on the CPU .

但上下文窗口开多大为宜呢？系数位编码系统有效减少了编码时钟周期数，并在FPGA上进行了功能验证。

The novel context window bit-parallel coding system improves the system performance significantly by reducing the number of clock cycles , and it was verified on FPGA .

阵列的时钟周期长度大致是两个单位全加器延迟，n位模乘法的计算延迟是2n+2个时钟周期。

The time to calculate a modular multiplication is 2n + 2 cycles , where n is the word length , and the clock delay is roughly the delay time of two full adders .

MIPS流水线的设计目标是要达到平均每个时钟周期完成一条指令，这就是流水线的极限速度。

The aim of MIPS pipeline is that one instruction completed in one period averagely .

假设高信号使能，计数器每个时钟周期进行计数，PWM输出的频率为时钟频率的2次幂分频。

Suppose that Enable is high , the counter counts up every clock cycle , and the frequency of the PWM output is the clock frequency divided by2 count bits .

本文讨论这样一款DSP，它采用分簇的VLIW体系结构，能够在单个时钟周期同时执行多个操作。

In this thesis we discuss such a DSP , which uses a clustered VLIW architecture and can perform multiple operations simultaneously during a single clock cycle .

通过模块级验证和在X微处理器中进行的系统指令级验证表明浮点除法部件满足设计要求，完成一次除法运算和平方根运算分别只需要39时钟周期和70个时钟周期。

Models simulation and system instructions verification prove that the implementation is valid and conform to the specification of X microprocessor , and 39 cycles and 70 cycles are needed for division instruction and square root instruction individually .

仿真结果表明，该并行结构能够在2n+1个时钟周期内完成n阶矩阵求逆，而传统的串行计算至少需要n3个时钟周期。

The result shows this parallel structure can finish n-order matrix inverse calculation in 2n + 1 clocks , but traditional serial computation needs n ~ 3 clocks .

与整数象素运动估计的架构相比，这种架构采用两个并行的PE阵列，在相同时钟周期内可以实现亚象素最佳匹配，并具有结构简单、易于实现的特点。

Compared with the system of integer pixel , this one , which is simple-structured and easy to realize , adopts two parallel PE arrays , and obtains the best-matched half-pixel block in the same time circles .

该原型支持39条指令，除DES、AES和正规基乘法MMU外其它指令都在一个时钟周期完成。

The prototype supports 39 instructions ; the executive cycle is one clock per instruction except DES , AES and MMU ( normal basic multiplication ) .

传统RISC处理器体系结构和编译优化技术主要专注于开发程序执行中的指令级并行性，通过在一个时钟周期内发射多个操作来提高处理器的IPC。

The traditional RISC processor architecture and compile optimizing technique was focus on exploiting the ILP , improving the IPC of processor through issuing multiple operations in one cycle .

NiosⅡ处理器支持256个具有固定或可变时钟周期操作的专用指令，设计者能用这些指令来加速实际要求严格的代码段。

Nios ⅱ processor is a special directive which supports 256 with fixed or variable clock-cycle operation . Designers can use these directives to accelerate the practice-strict code .

通过有限状态机对流水线的控制，在若干个时钟周期内完成了Java智能卡虚拟机（JCVM）的中等复杂指令的处理。

Control of the pipeline stages by a finite state machine allows execution of moderately complex Java card virtual machine ( JCVM ) instructions within several clock cycles .

通过合理安排时钟周期数和简化各周期内的操作，使1DDCT/IDCT模块能在八个时钟周期内快速完成一次变换。

After the number of clock cycle has been properly lengthened and the operations during the cycle simplified , the 1D DCT / IDCT can be executed within 8 clock cycles at high speed .

通过优化，使得编码一个10ms（80个采样点）的语音帧，所需的时钟周期仅为517573个。

After optimization , the clock cycles taken to encoder a 10ms speech frame ( 80 samples ) is only 517573 .

所有的寄存器都直接与算逻单元（ALU）相连接，使得一条指令可以在一个时钟周期内同时访问两个独立的寄存器。

All the 32 registers are directly connected to the Arithmetic Logic Unit ( ALU ), allowing two independent registers to be accessed in one single instruction executed in one clock cycle .

本设计的关键点为指令执行状态级的设计，每个指令周期包括8个机器时钟周期，由取指、译指、执指、RAM读、寄存器写、RAM写等组成；

The key of this design is the design of instructions state machine . Every instruction cycle includes 8 machine clock cycles , is made up of fetch instruction , decoder instruction , execute instruction , writing RAM , writing register and reading RAM etc.

不像CISC处理器，一般的RISC引擎执行在一个时钟周期，每个指令，在快上具有相同的时钟速度的CISC处理器执行一般的结果。

Unlike CISC processors , RISC engines generally execute each instruction in a single clock cycle , which typically results in faster execution than on a CISC processor with the same clock speed .

实验结果显示：芯片完成一次1024b的模幂运算需要约1.2M个时钟周期，而芯片规模在54K个等效门以下；

The experimental result shows that a 1024-bit modular exponentiation calculation can be performed in about 1.2 mega cycles , and less than 54K gates are needed .

本文提出基于KOA方法的多项式模乘，采用迭代二分法的思想，减少操作数的位数，降低实现的复杂度，只需9个时钟周期完成233位多项式乘法。

KOA method based on the divide-and-conquer approach is presented to reduce complexity by shorten the bits of operands . By this means , the multiplication result of two 233 bit 's operands is worked out in 9 clocks .

为了提高译码速度，对Viterbi算法的瓶颈所在ACS单元使用流水线和块处理的方法，使得反馈环的处理可以在多个时钟周期里完成。

In order to increase the decoding speed of the input encoded data , the pipelining and block processing methods are employed in the ACS unit that is the bottleneck of the Viterbi algorithm , so that the operation of the feedback loop could be completed in several clock cycles .

高效的解码器架构设计，使得每一个时钟周期可解码1bit的语法元素，与软件和现有解码器相比提高了解码速度。

The high efficient decoder architecture make it possible that 1 bit syntax element can be decoded in one clock cycle , and the decoding speed improved compare with current decoder and software .

每个解码输出在一个全时钟周期内保持高电平。

Each decoded output remains high for one full clock cycle .