芯片尺寸

芯片尺寸封装（CSP）技术

The Chip Size Package Technology

随着功率MOSFET的工作电压和电流大幅度增加、芯片尺寸的不断减小，导致功率MOSFET器件芯片的内部电场进一步增大。

With the increase of working voltage / current and the decrease of the chip size , the internal electric field of power MOSFET rapidly increased .

MEMS圆片级芯片尺寸封装研究

Study on Wafer - level Chip Scale Package for MEMS

步入主流技术的芯片尺寸封装（CSP）技术

Chip-size-package Technology Moves into the Mainstream

先进的芯片尺寸封装（CSP）技术及其发展前景

CSP technology and its development foreground

芯片尺寸封装（CSP）技术是近年来发展最为迅速的微电子封装技术之一。文章介绍了目前出现的四类CSP结构形式，分析了每种结构的工艺技术特点及其制作方法

Chip scale package ( CSP ) is a new microelectronic packaging technology rapidly developed in recent years Four types of CSP devices are described and fabrication technologies for each of them are analyzed in the paper

本文介绍了最新的超薄叠层芯片尺寸封装（UT-SCSP），它是CSP封装与叠层封装相结合的产物。

In this paper , the latest type UT-SCSP is introduced . It is the result of combining the CSP with the stacked package .

最后通过实验，得到不同因素下FITC染剂的聚集宽度，进行数据分析，从而得到最佳的检测芯片尺寸。

Finally , the FITC dye focusing width in different factors can be given by-experiment , and the data analyzed to get the best size of the detection chip .

SoC设计的高难度、高成本使设计者都面临这样的挑战：怎样在更小芯片尺寸上，以更低的功耗、更短的时间设计出功能更强大的芯片。

The complexity of SoC make the design and manufacture cost grow dramatically . Chip designers are facing with the challenge of how to design more powerful chips which are smaller in size , lower in power consumption in a shorter time .

圆片级芯片尺寸封装（WL-CSP）工艺是在固态芯片尺寸玻璃外壳中装入芯片。

This wafer level chip size package ( WL-CSP ) process encases the die in a solid die-size glass shell .

概述了芯片尺寸封装（CSP）的基本结构和分类，通过与传统封装形式进行对比，指出了CSP技术具有的突出优点，最后举例说明了它的最新应用，并展望了其发展前景。

Basic structure and classification of chip scale package are summarized in this paper , and its excellent merits are also indicated by comparison with traditional packaging styles . At last , new applications and development foreground of CSP are introduced through some examples .

晶圆级芯片尺寸封装（WCSP）消除了类似传统的芯片键合、引线键合和倒装芯片贴装过程的封装工序。

Wafer chip scale packaging ( WCSP ) eliminates conventional packaging steps such as die bonding , wire bonding , and die level flip chip attach processes .

综述了圆片级芯片尺寸封装（WL-CSP）的新技术及其应用概要，包括WL-CSP的关键工艺技术、封装与测试描述、观测方法和WL-CSP技术的可靠性及其相关分析等。

The wafer level packaging ( WL-CSP ) technologies and their application progresses , which including the key technologies of WL-CSP , the package test description , the observation method and the reliability the analyses of WL-CSP are summarized .

芯片尺寸为2.43mm×1.85mm。

The chip size is 2.43 mm × 1.85 mm .

芯片尺寸封装工艺技术

A Summary of the Process Technology for Chip Scale Package

所以分辨率要求越高，所需的芯片尺寸要随之增大。

So the higher resolution requirements , the bigger the required chip size increases .

超薄型圆片级芯片尺寸封装技术

Ultrathin Wafer Level Chip Size Package Technology

芯片尺寸、功耗的不断减少和芯片成本的不断降低是集成电路设计的基本目标。

The continuous decreasing of cost , size and power dissipation is the develop trend of IC design nowadays .

对于桌面和服务器应用，这意味着在大约同样的芯片尺寸上你可以放置更多的“速度”，结果带来显著的性能提升。

For desktop and server applications , this means you can pack more " speed " into a chip of roughly the same size , resulting in the well-known performance increases .

但是，随着芯片尺寸的减小，体积发热热通量的增大，对于芯片而言工作温度不断升高将造成芯片的不可逆损坏，更有甚者将导致整个微电子系统的崩溃。

But with the reducing size and the increasing heat flux , chips in terms of the rising temperature will cause irreversible damage . Moreover , the entire electronic system will even collapse .

由芯片尺寸计算得到最佳曝光场尺寸，使其最接近于光刻机提供的曝光场最大尺寸，提高了曝光系统的利用率；

The size of the best exposure field is calculated from the size of the chip , extremely close to the maximum size of the exposure field of the lithographic machine , so the utilization ratio of exposure system is increased .

在六月份的一份公告中，约翰逊和英特尔的其他代表们详细阐述了随着承载重要计算能力的芯片尺寸缩小到几乎可以忽略不计，移动计算能力可以从平板电脑和智能手机发展到其它物品上的可能性。

During the June announcement , Johnson and other company representatives drove home the idea that the possibilities for computing applications grow exponentially as the size of meaningful computing power approaches zero , creating opportunities for mobile computing that go far beyond the tablet or smartphone .

然而，当前通过减小单位像素尺寸或增大感光器芯片尺寸的硬件方案都存在技术上的瓶颈，同时价格昂贵的高精密感光器不适合于普及应用。

At present , however , it is impossible or hard to break the bottleneck by hardware schemes , such as reducing the pixel size or increasing the chip size . In the meanwhile , prices of expensive high precision sensor are not applicable to wider applications .

另一方面，使用OPC提高了工艺窗口，降低了整个芯片特征尺寸的变化，潜在地提高了集成电路的生产成品率。

Second , it increases the process latitude , decreases the variations of linewidth across a chip and could potentially enhance yield .

由于SoC集成度的不断提高以及芯片封装尺寸和管脚数量的限制，传统的调试方法现在已经不能满足嵌入式软件调试的要求。

Since the SoCs have integrated more and more units , and due to the limitation of SoC 's footprint and pin numbers , the traditional debugging methods are obsolete and unable to be any help .

所选用的CCD芯片像元尺寸为23μm×23μm，像元数384×288，全视场内混色光点列图能量重心偏最大值1.6μm，对应于4.39角秒。

Total number of elements of selected CCD is 384 × 288 , pixel size 23 μ m × 23 μ m. Maximum energy centre deviation in FOV for polychrome spot diagram is 1.6 μ m , corresponding to 4 . 39 ″ .

减小缩小芯片大小尺寸和使用300mm晶圆将实现的生产率力增长提高是内存产品芯片生产成本大幅度下降的关键基础。

The expected productivity increase by shrinking the chip size combined with the use of300mm wafers is the basis for a significant reduction of production cost per chip .

随着芯片特征尺寸的降低，金属互连中的电阻和寄生电容成为限制芯片性能的一个主要因素。

With scaling down of feature sizes of chips , the electrical resistance and parasitic capacitance have become a major factor that limits the performance of chips .

模拟结果显示，耦合效率的大小由光纤位置、芯片透镜尺寸和激光光源光斑形状共同决定。

The simulation results show that the optical coupling efficiency is determined by fiber position , the lens design of the photodiode chips , and the shape of the light source .

随着集成电路芯片特征尺寸的缩小，芯片制造业对晶圆表面洁净度的要求越来越高，这使得湿法工艺，即湿法刻蚀和湿法清洗工艺在集成电路生产中扮演着越来越重要的角色。

With scaling down of transistor , the requirement of cleaning on wafer surface is getting critical . It makes wet process i.e wet etch and wet cleaning are considered more and more important process in semiconductor manufacturing .