视频解码器

基于FPGA的数字高清晰度电视视频解码器的设计和实现

The design and implementation of an FPGA-based digital HDTV video decoder

MPEG-2视频解码器的FPGA设计

FPGA Design of MPEG-2 Video Decoder

图像采集子系统实现焊缝图像的采集与转换，主要由CCD视觉传感器和视频解码器组成。

Image capturing system finishes the task of capturing and converting image . It is composed of CCD and decoder .

HDTV视频解码器中系统控制的分析与实现

Study and Realization of system controls in the HDTV video decoder

HDTV视频解码器中码率缓冲的实现方法

Implementation of bit - rate buffering in HDTV video decoder

MPEG-4音视频解码器实时嵌入式设计

Real-Time Embedded Design of MPEG-4 Audiovisual Decoder

MPEG-4视频解码器一致性测试

Conformance test of MPEG-4 video decoder

由CCD摄取的图像，经视频解码器处理后再传给车辆识别系统进行图像的车辆识别判断。

The image absorbed by CCD bequeaths the vehicles recognition system after video frequency decoder processing to carry on the vehicles recognition judgment .

HDTV视频解码器输入缓存及系统控制单元的研究

A study on the input buffer and system control unit in HDTV video decoder

一种基于数据流的HDTV视频解码器

An HDTV video decoder based on data flow

以一个视频解码器为例验证了该映射算法的可行性，并给出了FPGA布局结果的实现示例。

The experiment with a video object plane decoder demonstrated the efficiency of the algorithm . An FPGA implementation example of placement result is given .

基于ARM7的MPEG-4视频解码器的优化

Optimization of MPEG-4 video decoder based on ARM7

AVS视频解码器的一种结构设计与硬件实现

Decoder architecture and hardware implementation for AVS-video

基于时间-调频率分布的多目标ISAR成像分布式视频解码器端的码率估计算法

ISAR Imaging of Multiple Targets Using Time-Chirp Distribution Rate Estimation Algorithm for Distributed Video Coding on Decoder

基于高速A/D和FPGA，提出了针对PAL制黑白全电视信号的视频解码器的设计方案，实现了实时图像信号的采集。

Based on high-speed A / D and FPGA , the scheme of a video decoder aiming at PAL black-and-white video signal is proposed , and in this way , the real-time image is captured .

算法研究与HDTV视频解码器硬件研制紧密结合，为国家重大项目－HDTV功能样机研制直接提供算法支持。

Researching algorithms combined with researching hardware of HDTV video decoder closely , which will directly offer algorithms support for researching of and implementation of the national project-HDTV function prototype directly .

现在MPEG-4视频解码器已经可以在Blackfin处理器上实时解码，图像分辨率达到D1（720x576）。

Now the embedded MPEG-4 decoder can work in realtime on the Blackfin processor , the image resolution achieves D1 ( 720x576 ) .

因此，在多媒体应用日益广泛，网络承受的通信压力日益增大的背景下，高效的AVS视频解码器的研究有重要意义。

Therefore , under the background of increasingly widespread application of multimedia and increasing of communication pressure that internet endures , the research for efficient AVS video decoder has great significance .

通过对AVS视频解码器逻辑资源和存储器的需求分析，选用了Altera公司单片高端大容量FPGA，克服了多片小容量FPGA带来的I/O紧张问题。

With analysis for the logic resources and memory requirements of AVS video decoder , a single high-end high-capacity FPGA from Altera Corporation was selected to overcome I / O shortages brought by small-capacity multi-chip FPGAs .

DSP视频解码器的实现，不仅可以应用在IP机顶盒上，还可以移植到便携式媒体播放器（PMP），视频会议终端，监控终端等，应用范围非常广泛。

DSP video decoder realization , not only apply on the IP set-top box , but also can transplant to the portable media player ( PMP ), the video conference terminal , the surveillance terminal and so on , the application scope is extremely widespread .

实现结果表明，该AVS视频解码器实现结构能在54MHz时钟频率下完成对25帧/s、720×576、4∶2∶0格式AVS码流的实时解码。

The implementation results show that the architecture for AVS video decoder can satisfy real-time decoding of 25 frame / s , 720 × 576,4 ∶ 2 ∶ 0 AVS video at the clock frequency of 54 MHz .

在深入研究AVS标准参考软件的基础上，完成了AVS视频解码器的框架结构设计，给出了一种C语言实现方案。

Based on the further study of AVS standard reference software , it completed frame structure design of AVS video decoder and provides an implementation plan of language C.Next , it gives a detailed analysis about AVS integer inverse transform and realization of interframe prediction algorithm .

其次对硬盘节目播放的功能模块作了简单介绍。再次对硬盘节目播放功能的实现作了详细介绍，其中包括MPEG-2原理、视频解码器、音频解码器和系统结构及其实现。

It also gives brief introduction of the hard disc program display function module and detailed analysis of the hard disc program display functions which include MPEG-2 theory , video decoder , audio decoder and system structure as well as how they perform .

在嵌入式操作系统平台下，摄像头模拟信号通过视频解码器进行数字化，经处理器转换为适合观看的格式，之后图像经压缩成MPEG-4格式，数据流通过CDMA无线模块发送。

In the embedded operating system platform , Analog camera signals were digitalized by a video decoder , and converted into suitable size for viewing by the processor . Then the video was compressed into MPEG-4 format . Data stream was sent out through the CDMA wireless module .

在接收端，视频解码器仅需要Sub-GOP中的某一帧的分组就可以解码并显示该帧。

At the receiver end , to decode and display one frame in the Sub-GOP , the video decoder only needs packets belonging to this frame .

视频解码器中插值与加权预测的硬件实现

Hardware Implement of Interpolation and Weighted Prediction in Video Decoder

视频解码器中多路并行输出的硬件实现

The Hardware Implementation of Multi-channel Parallel Output in Video Decoder

基于视频解码器的图像卡设计

Design of a video card based on video decoder

本文提出了一种高速视频解码器的软硬件协同设计方法。

A Co-design method for high-speed video decoder is present in this dissertation .

分布式视频解码器端的码率估计算法

Rate Estimation Algorithm for Distributed Video Coding on Decoder