时序逻辑

基于Matlab的时序逻辑电路的实验教学探索

Experiment Teaching Exploration of Sequential Logic Circuit Based on Matlab

时序逻辑电路的Petri网分析方法

Analysis of sequential logic circuit based on Petri net

面向投影时序逻辑的Web服务模型检测

Projection Temporal Logic Oriented Model Checking for Web Services

NL：松弛时序逻辑自然推理系统

N_l : a loose natural deduction system of temporal logic

冲压液压机PLC程序设计中的时序逻辑对象封装

Succession Logic Objects Encapsulated in PLC Programming of Hydraulic Stamping Press

符号模型检验（symbolicmodelchecking）是时序逻辑模型检验的技术一种具体方法，它使用一种更为有效的符号的方法来表示被检验系统，因而可以处理更大规模的系统。

Symbolic model checking method uses a more efficient " symbolic " representation for the system .

《时序逻辑电路》CAI课件的设计及实现

Design and realization of CAI courseware for clock and logic circuit

建立了CA认证系统的软件体系结构模型：使用时序逻辑语言XYZ/E，描述了CA认证系统体系结构；

It describes the CA attestation system architecture in the temporal logic language XYZ / E.

下位机用硬件描述语言在FPGA中实现多种串行接口的访问时序逻辑。

A multiple serial communication interfaces are implemented in a FPGA device with Verilog language .

UML活动图的时序逻辑语义

A Temporal Logic Semantics for UML Activity Diagrams

分析了AgentGrid中实体agent的模型，并利用分枝时序逻辑对其心智状态进行了形式化描述；

The model of entity agents in Agent Grid is analysed and its mental states is elaborated formally by using branching-time logic .

SPIN在同步时序逻辑中的应用

Application of SPIN in Synchronous Sequential Logic Circuits

采用FPGA实现喷头时序逻辑，既提高了设计的可靠性，又便于调试。

With FPGA technique to design sequential logic , the reliability is increased and the debugging becomes easy .

一种不确定时段的扩展时段时序逻辑：时间Petri网模型表示和线性推理

Extended Interval Temporal Logic for Undetermined Interval : Modeling and Linear Inference Using Time Petri Nets

PCI总线的接口设计、FPGA时序逻辑是本设计中的重点和难点。

PCI bus interface design , FPGA timing logic is the emphasis and difficulty in the design .

基于时序逻辑和SCR方法的需求分析方法

Requirements Analysis Method Based on Temporal Logic and SCR Method

CSCW时序逻辑模型交互行为的正确性研究

Study on Correctness of Interaction of Temporal Logic Mode of CSCW

利用PLA设计时序逻辑电路

A Design for Combinational Logic Circuit Using PLA

应用DT触发器的时序逻辑电路的设计方法

Design Method of Sequential Logic Circuits Using DT Flip - Flops

系统采用FPGA技术实现了CCD时序逻辑控制，CCD图像信号的采样和存储控制；

Based on FPGA technology , the system realizes CCD time sequence logical control , CCD image data sample and store .

基于中介逻辑对时序逻辑进行多值扩充，建立了一种中介时序逻辑系统MTL（MediumTemporalLogic）。

The authors have extended tempo-ral logic to a system of MTL ( Medium Temporal Logic ) based on the medium logic .

但是传统的串空间不能刻画P刚刚说过X，X是新鲜的这样的断言，而时序逻辑则适合刻画这样的断言。

But the traditional strand space cannot depict characterization of P said just X and X is fresh ,, and temporal logic is suitable for such an assertion .

FPGA时序逻辑设计则完成了等效采样逻辑、实时采样逻辑、数据存储搬运逻辑等内容。

FPGA sequential logic design section which includes the equivalent sampling logic , real-time sampling logic , and data storage handling logic is completed .

论文给出了用FPGA进行时序逻辑设计的基本原理图和Verilog程序。

The schematics and Verilog source program of timing logical design using FPGA are presented in the paper .

目前常用的形式化方法包括：有限状态机、Petri网、时序逻辑、通信进程演算和Z语言。

The formal methods include : finite state machines , Petri nets , temporal logic , communication process calculus and Z language .

RTL综合系统设计中时序逻辑综合的实现方法

Realization of Sequential Logic Synthesis in RTL Synthesis System Design

论文完成了系统的硬件设计、FPGA时序逻辑设计、ARM-Linux软件设计。

It completes the system hardware design , FPGA sequential logic design , ARM-Linux software design .

CPLD时序逻辑控制模块为外扩的存储器与DSP核心处理器之间提供系统正常读写的数字时序逻辑控制。

CPLD sequential logic-control module offers digital sequential logic-control for normal read and write of the system for expanding memory and DSP core processor .

时序逻辑综合是RTL综合系统设计中的一个重要部分。

Sequential logic synthesis is an important part of RTL synthesis system design .

软件设计包括：CMOS图像传感器寄存器配置、图像解码器、地址译码器、时序逻辑控制及寄存器控制。

The software design including : CMOS image sensors register configuration , image decoder , address decoder , timing logic control and register control .