缓冲存储器

可以在高速缓冲存储器策略中使用这个信息头来构建ID，而不必解析SOAP消息。

This header can be used in a cache policy to build IDs without having to parse the SOAP message .

高速大容量FIFO缓冲存储器设计

Design of high speed and large scale FIFO cache memory

这一页存入高速缓冲存储器了。

This page is cached .

FIFO缓冲存储器的结构及应用

FIFO memory buffers : structure and applications

数据采集部分主要由基于微处理器Z8018010PSC的多道（256道）脉冲幅度分析器与多道缓冲存储器MCB组成。

Data-collecting part mainly includes 256-channel pulse-height analyzer and multi-channel buffer .

CAMAC双数据缓冲存储器

Double Data Buffer Memory & A CAMAC Module

使用FIFO存储器作为A/D转换数据的缓冲存储器。

The first-in first-out memories ( FIFO ) are used as the buffer memories for the data of A / D conversion .

通过在高速缓冲存储器内使用双端口SRAM，使其具有真正双端口并行访问能力，提高了处理器内核的数据吞吐能力。

With the utilization of dual-port SRAM , the data cache is dual ported to allow two accesses to proceed in parallel .

SDRAM作为雷达光栅显示视频帧缓冲存储器，通过FPGA器件实现对SDRAM的控制，已成功应用于一款雷达光栅显示终端。

This article introduces that in a new design of radar raster-displaying terminal , SDRAM is used as video frame memory and FPGA is adopted to carry out the process of control circuit .

同步动态随机存储器（SDRAM）具有高速，大容量，价格低廉等优点，因而成为缓冲存储器的首选，但是SDRAM控制时序比较复杂，不能与DSP直接接口，这极大地限制了它的广泛应用。

The SDRAM has become the chief choice of the buffer storage because of its high speed , great capacity , and low price ; but due to its complex control timing , it cannot directly interface with DSP .

然后，可以使用cache-id从高速缓冲存储器中检索服务响应信息来使性能最优化。

The cache-id can then be used to retrieve service response information from the cache to optimize performance .

本文介绍了FIFO缓冲存储器的结构和性能，说明它如何扩大数据传输率，匹配不同的数据传输速率；

This paper makes an analysis of the structure of the FIFO memory buffer as well as its performances , with emphasis on explaining how it boosts up system performance by expanding the data transfer rate to match the different data transfer rates .

该处理机由16个处理单元和一个高速缓冲存储器组成一个一维线性阵列。

It consists of 16 cells and a cache connected linearly .

多机可缩放性高速缓冲存储器一致性协议分析

Analysis on Coincidence Protocol of Multi-CPU Machine 's Scaleable Cache

研究了这些算法和计算机芯片上纹理高速缓冲存储器的相互作用；

We will study how they interact with the on-chip texture cache .

32位微处理器的高速缓冲存储器和虚拟存储器

The Cache and The Virtual Memory in 32-bit Microprocessor

在高速缓冲存储器中找到所需数据。

The data needed is found in the cache .

区段相联缓冲存储器动态存储分配；动态存储器分配；动态存储区分配

Sector associative buffer storage dynamic storage allocation

应用程序存储区锁定区段相联缓冲存储器

Lock application memory sector associative buffer storage

在双微处理器的系统中，采用它作为数据交换的缓冲存储器可以简化电路设计。

It can be used for data exchange as buffer , it can simplify circuit design .

计算机高速缓冲存储器体系结构分析

Analysis of Computer Cache Memory Architecture

先进先出缓冲存储器

First-in first-out buffer memeory

高速缓冲存储器控制通信

Cache memory control communication

区段相联缓冲存储器传送／接收器缓冲区

Sector associative buffer storage

梯形图案数据缓冲存储器

Trapezoid pattern data buffer

解决处理器内核与访存之间的数据瓶颈，可以采用双Load/Store单元。为此，需要开发具有双端口访问能力的数据高速缓冲存储器。

Dual load / store units can be used to tackle the bottleneck between the processor core and the memory system .

光分组交换由于缺乏高速光逻辑器件、光缓冲存储器等，因此还处于研究阶段。

OPS still is placed in to study the stage because of lacking of the high-speed optical logic device and optical buffer .

并重点分析了进化存储系统中的关键技术，包括系统中内存管理的实现，高速缓冲存储器管理的实现和异构环境的数据共享。

Some key technique also is analyze , including Memory management realization this system , cache management realization and data share in the heterology environment .

用随机存取存储器的扇区存储因此能够访问磁盘的高速缓冲存储器。

A cache that stores copies of frequently used disk sectors in random access memory ( RAM ) so they can be read without accessing the slower disk .

本文论述了我们设计实现的有关高速缓冲存储器工作原理的教学动画演示系统。

In this paper , we discuss an animate-based courseware we designed and implemented , the Cache working principle teaching system made up of four parts : Cache working process module ;