导通电阻

通过改变MOS变容管的接入方法实现了更好的压控增益线性度，并采用了新的低寄生电容、低导通电阻的数控电容阵列结构来补偿工艺变化带来的频率变化。

A novel configuration of a MOS varactor is designed for good linearity of Kvco , as well as a new digital capacitor controlled array topology with lower parasitic capacitance and lower Ron .

一种新型的低导通电阻折叠硅SOILDMOS

A New SOI-LDMOS with Folded Silicon for Very Low On-Resistance

采用P型栅压自举开关补偿技术，可以有效地克服采样管导通电阻变化引入的非线性失真，提高采样精度。

By compensating with P-type bootstrapped switch , this circuit can overcome nonlinear distortion , which is generally introduced by signal-dependent on-resistance , and improve sampling resolution .

p埋层的辅助耗尽作用使漂移区浓度提高，从而使比导通电阻降低。

Owing to the assistant depletion effect of the buried p-layer , the concentration of n-type drift region is increased and the specific on resistance is thus reduced .

设计了一种采用饱和区MOS管作调节开关的电荷泵，通过控制饱和区MOS管的导通电阻来调节电荷泵的输出电压。

A charge pump with a MOSFET regulating switch working in saturation region was presented .

高温、高压LDMOS导通电阻的特性

Characteristic of on-state resistance of a high voltage LDMOS at very high temperatures

VDMOS击穿电压与导通电阻的最佳设计

VDMOS Optimum Design of Breakdown Voltage and on & Resistance

用阱作高阻漂移区的LDMOS导通电阻的解析模型

An Analytical Model of a LDMOS On-Resistance Using a Well as a High Resistance Drift Region

功率VMOSFET击穿电压和导通电阻的温度效应

Temperature Effects on Break-Down Voltage , on-State Resistance & Merit Figure of Power VMOSFET

JFET区电阻、沟道电阻、积累层电阻和漂移区电阻是导通电阻的四个最主要的组成部分。

JFET resistance , accumulation resistance , channel resistance and drift region resistance is the most important components of on-resistance .

通过三维仿真软件ISE分析，这种结构可以在低于40V左右的击穿电压下，获得超低的比导通电阻。

3D ISE simulation indicates that the ultra-low specific on-resistance is obtained with a breakdown voltage of less than 40V in FSOI-LDMOS .

IGBT在耐压和比导通电阻方面均有不错的性能，但是由于关断主要靠载流子的复合，关断速度慢始终是一个问题。

IGBT has excellent performance of both breakdown voltage and specific on-resistance . But the slow turn-off speed is always the problem when it is applied , since the removal of the carriers mainly depends on the recombination .

它是特别设计，在电压下降到0V时整个开关元件，同时保持良好的速度和导通电阻特性。

It is specifically designed to operate at voltages down to0V across the switch elements while maintaining good speed and on-resistance characteristics .

本文对CMOS模拟开关漏电流、导通电阻、电阻偏差，分布电容及外接负载等对模拟信号传输的影响进行了比较深入的分析，提出了改进开关性能的途径。

Effects of leakage current , on-resistance , resistor deviation , distributed capacitance and external loads of CMOS analog switches on analog signal transfer are analyzed in detail in the paper , and approaches have also been proposed to improve performance of the switch .

通过对计算数据的分析，指出了进一步提高效率的关键在于输出相同功率时降低功率管的电流峰值和有效值，减小绕组和MOSFET的导通电阻。

It is pointed out through the analysis of calculating data that the key to improve efficiency at the same output power is to decrease the peak current and rms current of power switches or the on-resistance of MOSFET and windings .

同步整流技术是开关电源领域近年来研究的新技术，也依赖于现今工艺的发展，功率MOSFET的导通电阻可以做得越来越小，使得功率损耗大大下降。

Synchronous rectification in the switching mode power supply is one of new technologies in recent years , thanks to the development of modern technology to make the power MOSFET on-resistance smaller and smaller . This makes the power loss significantly decreased .

然后采用ISE软件对器件特性进行模拟和验证，通过对器件耐压、阈值电压与导通电阻的模拟来对前面计算得到的各个器件参数进行优化，从而得到设计的最优值。

Then ISE software is used to simulate and validate the device characteristics . Through the simulation of the device voltage , threshold voltage and the resistance to optimize the values got by approximate calculation .

通过对PSJ比导通电阻的分析，得到了PSJ高压器件比导通电阻优化设计的理论公式。

Through analysis of the specific on-resistance of the PSJ device , a theory of PSJ optimization is developed .

仿真结果表明在埋氧层厚度1μm，漂移区厚度0.5μm时，该结构较常规SOI结构击穿电压提高了76%，比导通电阻降低了30%。

Numerical simulation indicates the breakdown voltage increases by 76 % and the specific on-resistance decreases by 30 % in comparison with that of conventional SOI structure at the 1 μ m buried oxide thickness and 0.5 μ m drift region thickness .

导通电阻模型考虑了LDMOS的沟道横向杂质分布和漂移区杂质纵向分布的结构特点，给出了导通电阻与杂质分布参数的明确函数关系。

In the model of on-resistance , we have considered the lateral doping distribution in LDMOS channel and vertical doping distribution in drift region . Then we provide the explicit dependence between on-resistance and doping distribution parameter .

传统垂直式DMOSFET高导通电阻的缺点在LDMOSFET中依旧存在，而垂直式IGBT关闭延迟和闩锁的现象，也在LIGBT中发生。

Problems with high on-resistance that are seen in traditional vertical structure DMOSFET still appear in LDMOSFET and phenomena of turn-off delay and latch-up are seen in LIGBT as well .

为了获得SOI-LDMOS器件耐压和比导通电阻的良好折衷，提出了一种漂移区槽氧SOI-LDMOS高压器件新结构。

In order to obtain good compromise of the breakdown voltage and the specific on-resistance of SOI-LDMOS , a SOI-LDMOS with trench oxide in drift region is proposed .

通过对测试结果的分析，进一步完善了整体功率VDMOS器件的导通电阻模型，并在此基础上，对集成功率VDMOS器件进行了进一步优化并提出漏极槽引出结构来进一步降低导通电阻。

Through the analysis of the test results , further improvement were adopt to fix the integrated power VDMOS device on-resistance model , and further optimized the structure of device in order decrease the on-resistance and increase the current capacity .

与传统的槽栅器件结构相比，新结构在相同的漂移长度和导通电阻下，击穿电压提高了30V，并表现出优异的频率特性。

Compared with conventional TG-LDMOS , the breakdown voltage of the new structure is improved by 30V with the same length of the drift region and on-state resistance , and the structure shows excellent RF characteristics .

分析了一个用阱作为耐高压漂移区的LDMOS的导通电阻，提出了带有场极板的高阻漂移区导通电阻的计算公式，改进了双扩散沟道导通电阻的计算公式。

A theory for an on-resistance of a LDMOS using a well as a high resistance drift region is developed . The calculation formulas of a drift region on-resistance with field plate are given , and also a calculation formula of a double-diffused channel on-resistance is improved .

具体研究内容如下：（1）导通电阻是功率UMOSFET的重要的性能参数，低压范围内（100V）不同耐压下导通电阻的最优化设计的结果会有所差别。

The detailed contents are described as following : ( 1 ) On-resistance is an important parameter of power UMOSFET , this paper study the differences of optimized on-resistance for low-voltage ( 100V ) UMOSFET under different breakdown voltage .

微电磁继电器的平面励磁线圈电阻约20Ω，外加5V电压时，微电磁继电器可实现吸合动作。吸合后，微电磁继电器的导通电阻为14.5Ω，继电器的响应时间为1ms。

Experimental result shows that when the micro electromagnetic relay in the resistance of the excitation coil of 20 Ω works at 5 V , its contact resistance is 14.5 Ω and respond time is about 1 ms under the electromagnetic actuation .

基于仿真结果首次讨论了GGNMOS的栅长对其一次击穿电压、二次击穿电压和电流、导通电阻、耗散功率等的作用。

Further analysis is conducted on the dependence of breakdown voltage , second breakdown voltage / current , turn-on resistance and dissipated power on gate length , based on MEDICI simulation .

VLT技术是一种可以同时大幅度改善击穿电压和降低导通电阻的新技术，但其难点在于从工艺上如何制造从源到漏逐渐变化的漂移区厚度。

VLT is a novel technology which can greatly improve the breakdown voltage and reduce specific on-resistance . However , the biggest challenge is how to manufacture the gradient drift region thickness increasing from the source to the drain .

另外本文对器件的工艺流程也做了简要的介绍。（2）提出可降低器件导通电阻的碳化硅GE-ACCUFET结构。

As the structure of GE-UMOSFET is different from conventional UMOSFET , the brief process of the device manufacture is proposed in this paper . ( 2 ) A novel silicon carbide GE-ACCUFET with low on-resistance is proposed .