引脚间距

CSP器件的引脚间距有0.8mm、0.75mm、0.65mm、0.5mm等。

CSPs lead pitches are 0.8 mm , 0.75 mm , 0.65 mm , 0.5 mm .

方差分析表明，芯片配重质量对1.0mm引脚间距PBGA器件焊点的可靠性有显著的影响，而焊盘直径和钢网厚度对可靠性无显著影响。

Chip weight has a significant effect on the reliability of solder joints , whereas pad diameter and stencil thickness have little effects on the reliability . These optimal combinations of process parameters have been applied to assemble the 1.0 mm pitch PBGA components .

为了能够满足产品小型化的要求，能够降低引脚针间距的芯片规模封装和倒装芯片技术，将永无止境地向前发展，精确贴装的能力将继续是一个非常重要的因素。

The capability for accurate placement will continue to be important as chip scale packages and flip chip technology reduce pin pitches even further in the unending race for product miniaturization .

随着VLSI技术向更大级集成和更高速度发展，使得I/O的数量急剧增加，引脚的尺寸和间距缩小，于是产品的检测变得更加关键。

As VLSI technology continues to evolve towards greater levels of integration and higher operating speeds , the I / O number of ICs increases and the dimension and pitch of pads shrinks , the test of these products becomes more and more important .

微处理器的时钟频率增加，引脚增多，引脚间距减少等问题也增大了传统调试方法的成本和难度。

Furthermore , the increasing of clock frequency and the number of pads , combined with the decreasing of the distance between pads and some pertinent problems could also result in the comparatively high cost and difficulty of traditional method .