锁相

本课题的研究重点就是AFM系统锁相检测设计与研究。

The important content of the thesis is the design and research of the phase lock system .

对主电路的工作原理进行了介绍，并详细介绍了CPU模块、锁相频率跟踪模块、恒振速控制模块、驱动信号输出模块、数字液晶显示模块的设计工作。

The block diagram of main circuit is discussed , and the design work of the CPU module , phase lock and frequency tracing module , constant vibration control module , driving signal output module and signal display module is also presented in detail .

基于相位噪声的锁相环IP核选择判据

The Selection Criterion of PLL IP Core Based on Jitter

调制器中采用预补偿的分数N锁相环。

A pre-compensation fractional-N phase-locked loop ( PLL ) is adopted in the modulator .

IC锁相环在脉冲占空比测量中的应用

Application of Integrated Circuit Phase-locked Loop in Measuring Pulse Duty Factor

具有锁频/锁频-锁相两种工作模式的CMOS数字锁相环

A CMOS Digital PLL with FL and FPL Lock Modes

一种采用新的相频检测技术的CMOS数字锁相环

A CMOS Digital PLL with a New Phase-frequency Detection Technique

毫米波Doppler锁相接收机

A mm-Wave Doppler Phase-Locked Receiver

而且选用的FPGA内部还具有锁相环的逻辑单元，为本次设计带来了很大的方便。

And the choice has PLL internal FPGA logic modules for this design brings great convenience .

基于FPGA的高性能全数字锁相环设计与实现

FPGA-based high-performance all-digital phase-locked loop design

锁相环用CMOS鉴频鉴相器及电荷泵的实现

CMOS phase-frequency detector and charge pump design for PLL

并设计了基于异步变频调制的三相数字锁相的方法和DSP控制的快速切换控制方法。

The DSP lock-in method based on the induction frequency modulation and fast switch control method is designed .

文中还对并联谐振逆变器的各种可能的工作状态进行深入了分析，指出为了保证其可靠运行并联谐振逆变器应工作小容性准谐振状态，采用了基于DSP的数字锁相控制策略；

, A digital phase lock loop is used to ensue the resonant inverter work in the desired state .

射频锁相环型频率合成器的CMOS实现

CMOS Implementation of RF PLL Frequency Synthesizer

一种低功耗射频CMOS电荷泵锁相环的设计

A Low-Power RF CMOS Charge Pump PLL

这是第一次在实际模型中发现非传统魔梯形式的V型阵发前奏锁相阶梯。

This is the first time to observe a prelude phase-locking staircase to type V intermittency with other forms .

单相UPS电源的锁相同步电路设计

Design of Phase-locked Synchronous Circuit in Single-phase UPS

锁相环在SDH网络中的应用

Application of PLL in Synchronous Digital Network over SDH

CDMA多目标遥测系统用微波锁相本振源的分析与设计

The Analysis and Design of the Microwave Phase-locked Frequency Source Used in CDMA Multi-target Telemetering system

一种UPS的数字化锁相及旁路检测和切换控制技术

Study of the bypass switching strategy and phase lock loop technique for fully digital-controlled UPS

基于锁相频率合成器的电压控制LC振荡器

A Voltage-controlled LC Oscillator With Integrated Frequency Synthesizer

介绍了一种应用于CCD彩色摄像系统的视频锁相同步系统。

This paper introduces the design and implementation of the video phase locked synchronism system for CCD color camera .

基于微波锁相环的Ka波段锁相信号源

Ka-band phase locked frequency source based on microwave phase locked loops

锁相环设计中采用差分调节的LC压控振荡器和全差分的电荷泵。

A differential tuned LC-VCO and a fully-differential charge pump are adopted in the PLL design .

高稳定特高频（UHF）锁相振荡源研究

The Study of Ultra-high Frequency High Stabling Phase-locked Oscillator

利用PWM整流器工作在有源逆变状态，并对逆变电流进行精确锁相控制，显著提高回馈到电网的电能质量。

PWM rectifier works in the inverter state , so it is used to feedback the energy to the power grid .

一种从E1信号中提取时钟的全数字锁相环

An All - Digital Phase Locked Loop for Clock Recovery from E1 Signal

锁相环（PLL）是当前实现时钟处理电路应用最为广泛的技术。

Phase-locked-loop ( PLL ) is currently the most wildly applied technique in CGU and CRC .

重点研究了基于FPGA的全数字锁相环频率跟踪技术和数字化SPWM实现技术。

All Digital Phase-Locked Loop frequency tracking and digital SPWM realization technology based on FPGA are emphasized in the research .

第五章主要讲快速自适应锁相环的FPGA实现，通过仿真和测试的结果说明该自适应方法的优越性。

In the chapter 5 the FPGA implementation of fast-adaptive phase-locked loop is introduced and the superiority of the adaptive method through simulation is showed .