低电平

基于FPGA的高频腔低电平数字控制系统

Low level digital control system of RF cavity based on FPGA

DE是高电平的时候，视频解码输出是有效的输出，当DE是低电平的时候，控制信号的解码输出是有效输出。

When the DE is high the pixel data is the valid output but when the DE is low the control data is valid output .

详细信息，参见IOLS静态低电平输出电流。

See IOLS static low-level output current for further information .

这是自动的情况下，如果设备不舒展SCL信号低电平期间。

This is automatically the case if the device does not stretch the LOW period of the SCL signal .

实验与仿真结果表明：该系统采用音频开关而不导致电机负载的音频噪声，同时使EMI能被限制在低电平。

Experiments and simulations show that the proposed system can operate in audio switch frequency range without audio noise from the motor load , meanwhile , EMI can be limited to low level .

在MOSFET漏端pn结泄漏电流的影响下，高温CMOS倒相器和门电路的输出高电平下降，低电平上升，导致了电路的功能失效。

It causes invalidity of circuit functions that high output voltage of high temperature CMOS inverter and gate circuits falls and low output voltage rises under influences of leakage current of MOSFET 's drain terminal pn junction .

在数字电路中，每个将高电平识别为逻辑l。把低电平识别为逻辑0的电路，被称为使用正逻辑。

In digital circuitry a circuit , which recognizes a high level to be a logical 1 and a low level as a logical-0 is said to use positive logic .

Keithley的《低电平测量手册》提供了关于使用同轴电缆和同轴三芯电缆的更多信息，包括低噪声电缆，以及电缆和连接器成套件。

Keithley 's Low Level Measurements Handbook provides more information about using coaxial and triaxial cables and connectors , including low noise cables , and cable and connector assembly .

为了提高测试精度，在进行电荷泵测试时，采用固定低电平与固定高电平相结合的方法，分别对SONOS器件源端和漏端进行注入电荷分布的测试。

To improve the precision of the actual measurement , a combination of a constant low voltage method and a constant high voltage method is introduced during the charge pumping testing of the drain side and the source side , respectively .

低电平宽量程电压信号的自动测量

Measure of the Electric Voltage Signal in Low Level and Wide Range

频谱仪测量低电平的精度研究

Accurate Study of Low Level Measurement on a Spectrum Analyzer

低电平电磁波辐射环境污染的动物实验观察

Observation on Low Electromagnetic Radiation Pollution in Animal Experiment

麦克风、电贝司（低音吉它）、和电子音响设备，特殊的也有低电平输出。

Microphones , bass guitars , and electric-acoustic instruments , also typically have low-level outputs .

本文主要研究触点带低电平负载时，继电器的动态接触特性。

This paper focuses on the dynamic contact characteristic of relay in low-duty load performance .

本节阐述可能影响低电平测量准确度的重要环境因素。

This section addresses important environmental factors that may affect the accuracy of low level measurements .

一种以相乘器为核心的低电平调幅电路设计

Design of Multiplier-centered Low-Electric-Level AM Circuit

高电平到低电平转换时间

High-level to low-level transition time

正确理解仪器的技术指标对于做好低电平测量工作是十分重要的。

Knowing how to interpret instrument specifications properly is an important aspect of making good low level measurements .

水平螺旋管逆流层析仪低电平电流型逻辑电路

Low-level current mode logic

对于其中的低电平控制系统，还详细分析了其中部分电路设计。

The low electronic level control subsystem , as an important part , its circuit design is analyzed concretely .

在每个系列中都有一系列电路将识别为一个高电平或低电平的电压。

Within each family there is a range of voltages that the circuit will recognize as a high or low level .

最后，讨论了频谱仪本地噪声对低电平信号测量影响的修正方法。

At last , correction method of low level signal measurement is discussed duo to effect of spectrum analyzer floor noise .

微材料力学性能测试是微机电系统设计制造过程中的重要环节，需要对低电平微弱信号进行高精度测量。

Micro material mechanical performance test is a fundamentality of design and manufacture for MEMS , high-accuracy measurement of weak signal is needed .

承载高测试电压的导体也应该采用屏蔽，以防止与邻近的低电平电路发生干扰。

Shielding may also be applied to a conductor carrying a high level test voltage to prevent interference with nearby low level circuits .

如果在多路扬声器中使用低电平电子分频器，则166XL应该放置在分频器之后。

If multi-way loudspeakers with low-level electronic crossovers are used , the166XL ( s ) should go after the crossover ( s ) .

开始送丝后，焊接电源输出低电平，熔滴依靠送丝动量向熔池过渡。

When the wire being stopping , the welding power outputs high level voltage with wire burning back and forming a liquid weld metal drop .

对于特定的信号类型，例如低电平或高频率，则不宜使用模拟背板，以避免造成信号劣化。

For certain signal types , such as low level or high frequency , the analog backplane should not be used to avoid possible signal degradation .

一旦累加结果溢出，就输出1（高电平），否则输出0（低电平）。

Every time the accumulator overflows , output a '1 ' . Otherwise output a '0 ' . That 's very easily done in an FPGA .

此外，其隔离受半导体器件漏流的限制，并且对低电平信号具有较高的插入损耗。

Also , their isolation is limited by the leakage currents of the semiconductor devices , and they have a high insertion loss for low level signals .

当输出低电平“0”时，环行分配器按反方向进行脉冲分配，步进电机反方向旋转。

When the voltage is " 0 ", the ring dividing driver shares the pulses according to the revert direction , the step motor runs in revert direction .