高电平

第一帧（8位）数据发送完毕时，各控制信号均恢复原状态，只有TI保持高电平，呈中断申请状态。

The first frame ( 8 ) data sending finished , the control signal are restored the original state , only keep a high level , TI application state interruption .

最后在CCS上设计并执行了一个独立工程，结果是引脚LOWPWR变为高电平，可以控制处理器在适当的时机进入深度睡眠模式或者唤醒。

Finally , an independent project is executed in the Code Composer Studio . The result is that the LOW_PWR pin is drivened to high level and the processor can be made to enter the deep sleep mode or wake up at appropriate moment .

DE是高电平的时候，视频解码输出是有效的输出，当DE是低电平的时候，控制信号的解码输出是有效输出。

When the DE is high the pixel data is the valid output but when the DE is low the control data is valid output .

在MOSFET漏端pn结泄漏电流的影响下，高温CMOS倒相器和门电路的输出高电平下降，低电平上升，导致了电路的功能失效。

It causes invalidity of circuit functions that high output voltage of high temperature CMOS inverter and gate circuits falls and low output voltage rises under influences of leakage current of MOSFET 's drain terminal pn junction .

在数字电路中，每个将高电平识别为逻辑l。把低电平识别为逻辑0的电路，被称为使用正逻辑。

In digital circuitry a circuit , which recognizes a high level to be a logical 1 and a low level as a logical-0 is said to use positive logic .

为了提高测试精度，在进行电荷泵测试时，采用固定低电平与固定高电平相结合的方法，分别对SONOS器件源端和漏端进行注入电荷分布的测试。

To improve the precision of the actual measurement , a combination of a constant low voltage method and a constant high voltage method is introduced during the charge pumping testing of the drain side and the source side , respectively .

每个解码输出在一个全时钟周期内保持高电平。

Each decoded output remains high for one full clock cycle .

因此，无需大静态高电平输出电流。

For this reason , a large static high-level output current is not required .

总线空闲时，两条线都是高电平（集电极开路）。

The bus is " idle " when both lines are high ( open-collector ) .

其余的都是高电平。

The rest will be high .

铁磁性拨叉相对磁导率的变化对高电平触发位置的影响可以忽略不计。

The influence of the fork 's permeability to the high level flip-flops position can be neglected .

高电平到低电平转换时间

High-level to low-level transition time

升压高电平时钟发生器

Boosted-high level clock generator

一个规定的高电平电压信号加到一个输入端时，流进该输入端的电流。

JEDEC ? The current into an input terminal when a specified high-level voltage is applied to that input .

接收器输入具有失效保护特性，当输入开路时，可确保逻辑高电平输出。

The receiver input has a fail-safe feature that guarantees a logic-high output if the input is open circuit .

在每个系列中都有一系列电路将识别为一个高电平或低电平的电压。

Within each family there is a range of voltages that the circuit will recognize as a high or low level .

系统就能运行在一个高电平状态下，或者破坏性信号到来时，系统会衰减它们。

The system can then be run at higher levels and will only be dropped back when damaging signals are present .

在+V和每根线之间连接着一个电阻，所以总线的空闲状态是高电平。

A resistor is connected between each line and + 5 V , so the idle state of the bus is high .

数据终端设备所控制的一种信号，当数据终端设备可以工作时，这个信号保持高电平。

A signal controlled by a data terminal equipment ( DTE ) that is held high while it is ready to operate .

一个有两个工作状态的电路或设备处于高电平状态或经常活动状态的时间百分比。

The percentage of time that a circuit or device with two operational states is in the higher level or more active state .

其二是同步信号检测电路，对多焦刺激器的场同步信号进行检测，包括电气隔离和高电平捕获。

The other part is simultaneous signal detecting circuit which is used to isolate the " Vertical Synchronous Signal " and capture its high level potential .

当键盘或者鼠标想发送数据时，它首先必须检查时钟线，确认它处于高电平。

When the keyboard or mouse wants to send information , it first checks the Clock line to make sure it 's at a high logic level .

此序列由16个固定宽度的高电平脉冲组成，两个相邻脉冲之间的低电平时间间隔是由伪随机数序列决定的。

The PRFM pulse sequence is composed by 16 fixed-width and fixed-amplitude short pulses , in which the duration between two neighboring pulses is determined by pseudo-random number sequence .

根据产品技术规范，随加到输入端的情况在输出端的电平，将在输出端建立一个高电平。

JEDEC ? The voltage level at an output terminal with input conditions applied that , according to the product specification , will establish a high level at the output .

若采样结果低于设定值，使单片机输出端口输出低电平，控制背光灯亮；反之，输出高电平，控制背光灯灭。

If the result is lower then preset value Low electric level is output through the output ports of the microcomputer to control backlight brightness , in reverse , electric level is output to control the brightness automatically .

本文论述在进行多通道并行同步数据采集或外部事件计数时，可应用软件扫描和逻辑判读高电平并累计其个数的方法。

In this paper , it is addressed that a software designed for scaning , logically judging , reading and counting high levels can be used for multiplex , parallel and synchronous data acquisition or counting of external events .

目前，二极管箝位式三电平逆变器中点电压平衡方法的研究已较为成熟，但对于更高电平数的逆变器，由于支撑电容的增加，其电压平衡控制也更困难。

Nowadays , the study of voltage balancing for Diode-clamped three-level inverter has been relatively mature . However , for the high number lever inverter , with the increase of support capacitors , the voltage balancing control is more difficult .

同时，送丝机构的控制系统与水下焊接专用电源相配合，停止送丝时，焊接电源输出高电平，焊丝返烧并形成熔滴；

The control system of the machine can work synchronously with the underwater welding power . When the wire being stopping , the welding power outputs high level voltage with wire burning back and forming a liquid weld metal drop .

接收管输出高电平给DC/DC，单片机检测到扣扳机信号，DC/DC输出驱动指令接通电磁阀，电击发一次。

The high level was outputted to DC / DC by received tube , the trigger signal was detected by the MCU , the driver instruction was outputted by the DC / DC to connect the electromagnetism valve , and the electric shock delivers once .

场发射平板显示高低压电平转换电路

A Low-high Voltage Level Shifter Circuit for FED Display Driver IC