指令级并行

实验结果表明，该框架很好地提高了指令级并行度（ILP），减少了指令执行时间。

The results of the experiment demonstrate that this framework can improve ILP efficiently , and reduce the execution time greatly .

文章概述了VLIW体系结构特征，分析了在VLIW体系结构下开发指令级并行性的技术难点，针对影响VLIW体系指令级并行性的因素阐述了一些基本的实现策略和实现技术。

This paper introduces the characteristics of VLIW Architecture , and analyzes the difficulties of exploiting ILP in VLIW architecture . According to the factors of infecting performance of VLIW architecture ILP , Some basic implementing strategies and technologies have been discussed .

C++编译器完成的循环展开可以公开更多的指令级并行，但也创建了更多活变量（livevariable），编译器需要使用它们来跟踪寄存器分配。

Loop unrolling done by the C + + compiler can expose more instruction-level parallelism , but can also create more live variables that the optimizer needs to track for register allocation .

为了充分利用VLIWDSP处理机的指令级并行性，必须使用软件流水技术对DSP程序进行优化。

In order to fully utilize the instruction level parallelism of the recent VLIW DSP processors , DSP programs have to be optimized by software pipelining .

在CPU的发展过程中，处理器研究人员利用超级流水线、超标量发射、乱序发射、动态转移预测等技术来实现指令级并行以提高单核心芯片的计算、处理能力。

For a long time , processor researchers use super-pipelined 、 superscalar launch 、 out-of-order emission 、 dynamic branch prediction and other technologies to improve the calculation and processing capacity of the single-core chip .

本文将从算法级并行处理、指令级并行处理与进程级并行处理等三个方面讨论嵌入式RISC体系结构的设计问题。

The design problem of an embedded RISC architecture in parallel processing of algorithm level , instruction level and process level is discussed in this paper .

传统RISC处理器体系结构和编译优化技术主要专注于开发程序执行中的指令级并行性，通过在一个时钟周期内发射多个操作来提高处理器的IPC。

The traditional RISC processor architecture and compile optimizing technique was focus on exploiting the ILP , improving the IPC of processor through issuing multiple operations in one cycle .

结点内并行的一种发展趋势是同时支持指令级并行和数据级并行，Stanford大学研制的Imagine流处理器是同时支持指令级并行和数据级并行的典型代表。

One of the trends of intra-processor parallelism is to support both instruction-level parallelism ( ILP ) and data-level parallelism ( DLP ) . The Imagine stream processor developed by Stanford University is an ILP-DLP representative .

图像处理算法的特点决定其是内在可并行的，这种并行粒度介于数据并行（DLP）和指令级并行（ILP）之间，称之为子字并行。

Image processing algorithms are inherently sub-word parallel ( SWP ), whose granularity is between data-level parallelism ( DLP ) and instruction-level parallelism ( ILP ) .

新一代面向密集计算的高性能处理器普遍采用分布式寄存器文件来支撑ALU阵列，并通过VLIW开发指令级并行。

Newly-emerging high performance processors for intensive computing generally use distributed register files to support ALU array and to explore instruction level parallelism ( ILP ) by VLIW .

不断挖掘指令级并行性（ILP）是提高处理器性能的关键，而分支跳转指令造成的控制相关，严重限制了ILP的开发。

Instruction level parallel processing is the key technology to improve the performance of current processors , while the control dependences caused by braches become bottlenecks of exploiting ILP .

围绕MMX技术，提出了面向数据流的并行程序开发方法，实现和测试了典型的多媒体数据处理算法，研究了指令级并行计算环境下不同算法的实现技巧，评估了各自的性能。

Based on MMX technology , a data flow oriented parallel programming method is advanced , the implementation techniques of 4 typical multimedia processing algorithms are demonstrated , and their speedup performances are tested .

本文结合指令级并行32位定点处理器的结构特点，对JPEG算法中DCT、量化及Huffman编码等步骤，提出一些适于并行处理算法和数据结构的优化方法，以有效发挥其高速并行的性能。

This paper describes some methods on optimizing parallel processing and data structure for DCT , quantization , and Huffman coding of JPEG algorithm with parallel instruction of 32 bits fixed point processors , in order to develop its parallel processing capability effectively .

OpenDivx是一种基于MPEG-4思想开发的视频压缩软件。为了解决嵌入式条件下视频数据的实时压缩问题，本文对OpenDivx视频编码程序进行了循环级并行性和指令级并行性的分析。

Open Divx is a video compression software based on MPEG-4.In this paper , in order to resolve the problem of real-time video data compression , we analyze the LLP ( Loop-Level Parallelism ) and ILP ( Instruction-Level Parallelism ) of the Open Divx video compression program .

CISC→RISC设计思想对DSP体系结构设计中数据和指令级并行性开发产生了深刻影响，融合RISC和SIMD技术的单核处理器已经成为DSP体系结构设计的新趋势。

This paper reviews the influence of transition from CISC to RISC on DSP architecture 's data level and instruction level parallelism exploitations and points out that the single core architecture combination of RISC and SIMD technologies has proved to be the new trends in DSP design domain .

光互连指令级并行计算结构模型

A New Instruction Level Parallel Processing Model Based on Optical Interconnection

控制投机和数据投机是提高程序指令级并行度的有效方法。

Control & Data speculations are effective ways to improve instruction level parallelism .

指令级并行之发展与展望

The Development and Prospect of Instruction - Level Parallelism

指令级并行程序执行模型

The model of instruction level parallel program execution

文章提出的优化技术分为两类：存储优化技术和指令级并行优化技术。

These optimization techniques fall into two categories : storage optimization and ILP optimization .

研究结果表明：采用指令级并行处理技术可以大大加快系统的处理速度，具有较大的实用价值。

Study result shows that technique of ILP may accelerate the data processing and have great practical value .

为了提高指令级并行，编译器必须进行大量的优化。

In order to improve instruction level parallelism , compilers tend to adopt more aggressive and complex optimization algorithms .

但是，单个程序的有限指令级并行性决定了多发射处理器的资源利用率不高。

However , the finite ILP in single program determines that the resource utilization of multi-issue processor is low .

一方面片上多处理器的发展使微处理器性能的提升由挖掘指令级并行性转变为开发线程级和数据级并行性。

On one hand , the performance gain of multiprocessor has changed from instruction-level parallelism to thread-level and data-level parallelism .

谓词是条件执行的依据，是提高指令级并行的新途径。

Predicate is a guard for predicated execution , which presents new approaches to promote instruction level parallelism . condition and implement the p.

讨论了指令级并行运算环境中多媒体数据处理的实现方法和性能。

This paper presents the implementation approach and the experimental results of multimedia realtime processing on the ILP ( Instruction Level Parallelism ) computing platform .

指令级并行处理是提高处理器性能的关键，而编译器在其中的作用是至关重要的。

Instruction-level parallel processing is the key technology to promoting the performance of current processor , and compiler plays a very important role in it .

近二十年来，指令级并行编译一直是工业界和学术界关注的热点，在这方面也已作了大量的工作，但许多问题仍未得到圆满解决。

In the past 20 years , a lot of work has been done in this area . But there are still problems remaining unresolved .

在微处理器中，为突破数据流限制以获取更高的指令级并行，指令值预测研究日益得到广泛重视，多种值预测器设计方案被提出。

In an effort to exploit instruction level parallelism in modern microprocessors , several schemes have been proposed using value prediction to exceed the dataflow limit .

同时本文提出的优化技术也为在编译系统中提高处理器的指令级并行性提供了参考。

At the same time , the optimization technique we proposed could be referred as an approach that improves the instruction level parallelism from the complier side .