多路选择器

这种单元的组合逻辑部分只采用了3个2选1多路选择器（2：1MUX）和两个功能增强的输入可反相编程的多路选择器（2：1EMUX），有效地节省面积和提高了速度。

The cell is only made up of three 2:1 MUX and two enhanced 2:1 MUX inverted by programming , achieves fast speed and costs little chip area .

利用布尔代数运算，导出了求布尔函数的简化的不相交SOP形式的一种代数方法，提出了基于这种SOP形式的数字多路选择器网络设计的一种代数方法。

By using Boolean algebraic operations , an algebraic method for finding the reduced disjoint SOP forms of Boolean functions has been developed and an algebraic method for designing the digital multiplexer networks based on the SOP forms is proposed in this paper .

采用FPGA作为主控芯片，在FPGA内部设计了刺激脉冲发生器，多路选择器和串并转换器。

It uses FPGA as its main control chip . The FPGA comprises a spike generator , a serial-to-parallel converter and some multiplexers .

针对数字电视通用调试、开发平台需要处理的各种信号源，设计了其中的灵活的多信号源处理模块，完成了多路选择器的FPGA实现。

Started from various signal sources the DTV needs to process , designs the multi signal source processing module and schemes out the multiplex controller on FPGA .

数字信号处理电路采用高精度、具有温度补偿的时钟芯片作为基准时钟，采用高频可逆计数器对整形后的脉冲信号进行正向或逆向计数，采用高性能的多路选择器控制两路SAW信号的定时选择。

In its digital processing circuit , clock chip with high precision and temperature compensation is uesd as reference clock . High frequency reversible counter is used to count trimmed impulse signal forward or backward and two pathes SAW signals are selected timely by multichannel selector .

用VHDL语言设计了硬件电路，具体包括端口控制电路、仲裁电路、时钟多路选择器电路、FIFO电路、核心控制电路、标志生成输出多路选择器电路；

The repeater controller of HUB is designed with VHDL , including port control circuit , arbiter , clock MUX , FIFO , core control circuit , and symbol generation & MUX .

用多路选择器实现组合函数

The use of multiplex converters for the realization of combinational functions

数字多路选择器树形网络设计理论和算法

Theory and Algorithm for the Design of Digital Multiplexer Tree-Type Networks

数字多路选择器单级及二级逻辑网络的最优化设计Ⅱ

Optimal Design for Digital Multiplexer Single-Level and Two-Level Logic Networks ⅱ

数字多路选择器网络设计的一种代数方法

An Algebraic Method for the Design of Digital Multiplexer Networks

利用谱方法的多路选择器树形网络设计

Designing of Multiplexer Tree-Type Logic Networks by Spectral Means

多路选择器二级逻辑网络设计

Design of Two - Level Logic Networks Using Multiplexers

一种共享打印机多路选择器的设计

A design for a printer - sharing multiplexer

通过多路选择器以及译码电路，系统可以采集多达32个电池的状态信号；

Through multiplexer and decoding circuits , the system can acquire signals of up to 32 cells .

这种方法可以使待设计的数字多路选择器网络简化到最小树形网络。

By using the method , the digital multiplexer networks being designed can be simplified to minimal tree-type networks .

利用多路选择器连接调制信号和载波信号，可以实现多种调制信号的仟意切换。

By using multi-route selector to connect modulation signal and carrier wave signal , random switching of multi-modulation signals can be realized .

然后给出利用多路选择器实现多变量组合函数时，获得最小或接近最小的树形结构网络的设计方法。

The design method , by which the minimization or near minimization of tree-type logic networks can be obtained , is presented when multiple variables combinational logic function is implemented by using multiplexers .

该芯片集成了6×6单元有源传感阵列、模拟多路选择器、输出缓冲器、参考源和数字控制电路，实现了传感电路和后端信号处理电路的单片化集成。

It is fabricated in a 0.6 μ m standard CMOS process , consisting of 6 × 6 active sensor array , analog multiplexer , output buffers , reference sources and digital controlling circuits .

引入多路选择器来加速实现任意位左移，在提高主关键路径并行性的同时，采用了多种方法对寄存器传输级代码进行优化。

Multiplexers are adopted to accelerate the left shift operation , and parallel processing based on data dependency is used to optimize RTL ( Register Transfer Language ) code to shorten the main critical path .

本文讨论组合函数的分解，给出组合函数利用多路选择器通用逻辑模块实现时，获得最小或接近最小树形结构网络的设计方法。

This paper discusses decomposition of combinational fuctions , and presents a design method by which the minimal or near minimal design of a tree type logic network realized by using multiplexer universal logic modules can be obtained .

该芯片上集成了8×8单元有源传感阵列、基准电压源、模拟多路选择器、输出缓冲器和数字控制电路。

A new array sensor chip for recording cell membrane potential is designed based on standard CMOS process . It consists of 8 X 8 active sensor array , reference voltage , analog multiplexer , output buffers and digital controlling circuits .

基于逻辑函数按变量展开式的分析，利用布尔代数运算，讨论了数字多路选择器二级逻辑网络的最优化设计的理论和方法。

On the basis of analysis of the expansion form for the logic functions with respect to its some variations , theory and method of optimal design for digital multiplexer two-level logic networks are discussed by using Boolean algebra operations in this paper .

在IEEE1149.1标准的基础上，用模拟多路分配器与选择器实现对模拟宏单元的隔离、控制与观察。

Based on the standard of IEEE 1149.1 , the isolating , controlling and observing of the analog macro are implemented through the employing of analog multiplexers .